1. Field of the Invention
The present invention relates to an IMOS transistor, IMOS standing for Impact Ionization Metal Oxide Semiconductor.
2. Discussion of the Related Art
FIG. 1 is a perspective view of an IMOS-type transistor formed in an SOI-type (Silicon-On-Insulator) wafer. The SOI wafer comprises a support 1, a thin insulating layer 2, and a semiconductor layer 3. An insulating layer 5 formed in through openings of semiconductor 3 surrounds a so-called “active” area 6 of semiconductor layer 3.
A lateral strip 10 of active area 6, shown to the left of the drawing, is doped with P-type elements. Another lateral strip 11, shown to the right of the drawing, is doped with N-type elements. A central strip 12 of active area 6, undoped or intrinsic I, is placed between lateral strips 10 and 11. The right-hand portion of central strip 12 is covered with a stacking of a thin insulating layer 15 and of a conductive layer 16.
FIG. 2 is a cross-section view of the structure shown in FIG. 1. P-type lateral strip 10 is connected to a source terminal S. N-type lateral strip 11 is connected to a drain terminal D. Conductive layer 16 is connected to a gate terminal G. The operation of this transistor is close to that of a reverse diode, the breakdown voltage of which can be varied. The diode in question is the PIN diode formed by strips 10 to 12. When the voltage of gate G increases with respect to that of central intrinsic strip 12, an N-type area 20 creates under thin insulating layer 15. This results in bringing P-type strip 10 “closer” to N-type strip 11 and thus in decreasing the reverse breakdown voltage of the PIN diode.
FIG. 3 is a diagram illustrating the variations of drain-source current iDS crossing the diode according to voltage Vg on gate terminal G. Current iDS is substantially zero for voltages Vg smaller than a threshold voltage Vt and substantially equal to a current imax when voltage Vg is greater than threshold voltage Vt. The drain-source voltage of a conventional MOS transistor according to its gate voltage is shown in dotted lines. As visible in FIG. 3, the increase in current iDS along with the gate voltage is much more progressive for a MOS transistor than for an IMOS transistor. IMOS-type transistors exhibit a smaller static power consumption than MOS transistors. Further, IMOS-type transistors are capable of switching, that is, of passing from the non-conductive state to the conductive state, within a very short time shorter than or equal to that of a conventional MOS transistor.
Further, a conventional method for forming an IMOS transistor such as that shown in FIG. 1 is to form the gate, that is, layers 15 and 16, then to perform a first implantation step for forming lateral N-type strip 11 and a second implantation step for forming lateral P-type strip 10. On forming of lateral N-type strip 11, it is necessary to mask the exposed portion of semiconductor layer 3 placed to the left of the gate. The opening of the mask formed above the area which is desired to be implanted, say the right-hand portion of the semiconductor layer, should not be shifted to leftwards by a distance greater than the width of its gate to avoid implanting the portion of semiconductor layer 3 placed to the left of gate 15/16. Now, current photolithography devices used for the manufacturing of integrated circuits do not enable aligning such an opening with an accuracy greater than 40/50 nm. The gate width of IMOS transistors can thus not be provided to be smaller than 50 nm. Now, it is possible to manufacture conventional MOS transistors exhibiting smaller gate widths. Accordingly, for an identical current capacity, an IMOS-type transistor such as that shown in FIG. 1 may be much more bulky than a conventional MOS transistor.